A physical layer of a computing device (“PHY”) is used for communicating between integrated circuits and external devices, such as other integrated circuits, typically through a data bus or a set of signal wires. The physical layer is typically configured to implement a desired communication protocol or specification that has been established for the particular application.
FIG. 1a illustrates a diagram of a physical layer of the prior art for communicating between a memory controller and an external memory device. A standard double data rate (“DDR”) PHY 12 interacts with an on-chip memory controller 10 and an off-chip dynamic random-access memory (“DRAM”) 22. The PHY 12 comprises a DDR physical layer interface (“DFI”) 14, first-in-first-out (“FIFO”) buffers 16, and address and data macros 18 for transmitting data between the FIFO buffers 16 and the DRAM 22. The memory controller 10 and the PHY 12 represent two primary design elements in DDR memory systems, which are used in virtually all electronic system designs, from cellphones and set-top boxes, to computers and network routers.
The DFI specification defines an interface protocol between the memory controller 10 and the PHY 12, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The DFI protocol defines the signals, timing, and functionality required for efficient communication across the PHY, which is known by a person having ordinary skill in the art. The DFI specification also allows the memory controller 10 to be operated at a same frequency as DRAM 12, or at half (or other fraction) of the frequency of the DRAM 12.
FIG. 1b illustrates a graph of clock signals for a physical layer interface of the prior art. A CLK_CTL clock signal is inputted to the memory controller 10 from the clock generator 20 for clocking the memory controller 10. A CLK_MEM clock signal is inputted to the address and data macros 18 of the PHY 12 for clocking the address and data macros 18 to receive data from and/or transmit data to the DRAM 22. The CLK_CTL clock signal and the CLK_MEM clock signal are plotted side-by-side along a time axis. The CLK_MEM clock signal can have twice (or another multiple of) the frequency of the CLK_CTL clock signal. Also, the CLK_MEM clock signal and the CLK_CTL clock signal are asynchronous signals. Thus, there is uncertainty as to alignment of the clock signals. Since the frequencies of the CLK_CTL signal and CLK_MEM are different, the FIFO buffers 16 are needed to buffer any data to account for this asynchronous.
The depths of logic in the PHY 12 and in the memory controller 10 are different, and, moreover, the logic may be operating at integral multiple frequencies, which prove to be challenging during integration. The width of the PHY 12 makes it even more difficult to align the clock signals, e.g., the CLK_CTL, CLK_MEM, and the CLK_DFI signal, for the respective logic and components.
Traditionally, the FIFO buffers 16 are employed to store data between the memory controller 10 and the DRAM 22 in the PHY 12. The memory controller 10 writes data according to the CLK_CTL signal edge. The PHY 12 can then read/write the data according to the timing of the CLK_MEM signal. Based on the type of command, the PHY 12 can read data from the DRAM 22 or write data to the DRAM 22. A clock generator 20 generates the clock signals CLK_CTL, CLK_MEM, and CLK_DFI according to the operating frequencies of the memory controller 10, the DRAM 12, and according to the DFI specification.
If a write command is given, the PHY 12 reads the data based upon the CLK_MEM signal, and routes the appropriate command and data. If a read memory command is given, the PHY 12 reads the data based on the CLK_MEM signal and sends the appropriate command and data. The PHY 12 also can read the data, sending an appropriate command, and wait for the data from the DRAM 22. Once the data is available, the PHY 12 writes the data to the FIFO buffers 16, and informs the availability of data to the memory controller 10.
There must be a significant number of FIFO buffers 16 in the PHY 12 to provide reliable operation due to the frequency ratio of the CLK_CTL and the CLK_MEM signals, and due to uncertainties between and among clock distributions for the various components of the PHY 12. Additionally, the minimum latency for reliable operation needs at least three additional cycles of CLK_MEM due to a clock domain crossing, which will increase the overall latency of the system and also increase the needed chip area. The depth of the FIFO buffers 16 also depends on the frequency ratio and the skew between the clock signals from the clock generator 20.
Therefore, there exists a need to provide new methods and systems for providing a PHY that can account for any frequency ratio, decrease latency, and reduce the amount of chip area used for the PHY. In particular, there exists a need to provide new methods and systems for a PHY that do not need FIFO buffers between a memory controller and an external memory.
Additionally, the PHY must evenly distribute a reset signal and the clock signals throughout the PHY and the memory controller. In order to keep the data in correct order, the reset signal must be simultaneously distributed throughout the memory controller and the PHY.
FIG. 7 illustrates a diagram of a distribution network of the prior art for distributing clock and reset signals. Typically, a DDR data macro can be 72 bits wide in depth, and 10 mm long in length. Due to its relatively extensive depth and length, clock distribution in the DDR macro is challenging in itself, and further difficult when trying to synchronize the signals for the DDR macro. Prior art uses two independent balanced distribution networks, one for a clock signal I_CLK and the other for a reset signal I_RESET, where both balanced distribution networks comprise a network of drivers, e.g., buffers, clock drivers, etc., for synchronously driving a clock signal.
For instance, the clock signal I_CLK is distributed to divider and counter blocks 30 via a first distribution network 28. Simultaneously, a clock signal I_RESET is also distributed to divider and counter blocks 30 via a second distribution network 26 to mirror the timing of when the I_RESET signal is received by each of the divider and counter blocks 30. Unfortunately, the second distribution network 26 consumes a great amount of chip area and consumes a great amount of power.
Therefore, there exists a need to provide new methods and systems for distributing clock and reset signals to reduce the amount of chip area used and to reduce power consumption for distributing the clock and reset signals.